As it is well known, the development of stacking technology for heterogeneous device integration has recently increased in importance.
Stacking of chips, in which two or more integrated circuits or ICs of different types are placed one on the top of the other in the same package, is an alternative to silicon integration and provides improvements at the system design level in terms of size, cost, speed, power consumption and ease of application for a wide variety of product.
However, a successful implementation of the stacking or 3D technology requires dealing with state-of-the-art of assembly processes such as wafer back-grinding, handling, die attach, wirebond and alignment. So, the choice of a stacking or 3D technology depends largely on the application of the final chip so obtained.
A correct and enhanced chip-to-chip communication in a stacked device is a fundamental feature to be guaranteed in stacked devices in the scenario of the so-called Systems-on-Chip and Systems-in-Package.
In fact, stacking integrated circuits or silicon structures inside the same package and making them communicate can enhance the performance of a digital system comprising such structures as a whole, as described in the article to Kaustav B. et al.: “3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration”, Proceedings of the IEEE, 89(5):602-633, May 2001.
Moreover, vertical data communication using AC wireless interconnect has been recently presented as a very promising stacking or 3D technology for high-bandwidth, high speed applications, as described in the article to Kanda K. et al. entitled “1.27 Gb/s/pin 3 mW/pin wireless superconnect wsc interface scheme”, ISSCC Dig. Tech. Papers, pp. 186-187, February 2003.
Also known from the article to R. J. Drost et al.: “Proximity Communication”, IEEE J. Solid-State Circuits, 39(9):1529-1535, September 2004, is a prototype based on vertical communication.
A chip-to-chip vertical communication system, as described in the above referred articles, is based on contactless 10 schemes exploiting capacitive coupling as an inter-chip channel. In particular, an upper metal layer of a technology process manufacturing the system is used to form a capacitive channel, as shown for instance in FIG. 1, the chip-to-chip vertical communication system being globally indicated at 1 and hereinafter called briefly the system 1.
As shown in FIG. 1, the system 1 comprises a plurality of communication units 2, each comprising a transmitter 3 and a receiver 4.
In particular, the transmitter 3 resides on a first chip A and the receiver 4 resides on a second chip B, the first and second chip A and B being assembled in a stacked or 3D configuration, the first chip A being on the top of chip B and the transmitter 3 and the receiver 4 being positioned on respective facing surfaces of the chips A and B, more particularly the transmitter 3 on a bottom surface of the chip A and the receiver 4 on a top surface of the chip B, with reference to an XYZ axis-system as shown in FIG. 1. Obviously, the above configuration (transmitter 3-chip A; receiver 4-chip B) is considered only as an example, a reverse configuration (transmitter 3-chip B; receiver 4-chip A) being also possible, the same consideration applying.
It should be emphasized that this approach requires on-chip communication circuits able to guarantee high performance, low power dissipation and reliable flexibility in data exchange.
The known communication circuits are substantially based on very simple driver models, but require sense-amplifiers and biasing blocks for the generation of internal voltage values, in particular in the receiver 4. So, these known communication circuits show a great power consumption due to short-circuit currents.
One technical problem underlying embodiments of the present invention is that of providing a chip-to-chip communication system having structural and functional characteristics which overcomes the limits which still affect the devices realized according to the prior art.